1. Technical Field
Various embodiments relate to a stacked semiconductor package, and more particularly, to a stacked semiconductor package including an interposer.
2. Related Art
A packaging technology for a semiconductor apparatus has been continuously developed with the demand for miniaturization and high capacity, and recently, there have been developed various technologies for a stacked semiconductor package capable of satisfying miniaturization, high capacity, and package efficiency.
The “stacking” in a semiconductor industry indicates a technology of vertically piling at least two semiconductor chips or packages, and in the case of a memory element, it is possible to obtain a product having a memory capacity larger than a memory capacity achievable in a semiconductor integrated process, and to improve the efficiency of use of a package area.
The stacked semiconductor package may include a package substrate, a plurality of semiconductor chips, and an interposer that electrically connects the package substrate to the plurality of semiconductor chips.
In the stacked semiconductor package with such a structure, when input/output pads of the plurality of semiconductor chips are tested using the interposer, loading occurring by the interposer increases and thus delay also increases in the input/output pads, resulting in the deterioration of a test result.